1. Field of the Invention
This invention relates to a driving circuit for a liquid crystal display, and more particularly, to a shift register employing an amorphous silicon thin film transistor that prevents a voltage at a node, which controls an output buffer, from being varied due to a parasitic capacitor of the thin film transistor.
2. Discussion of the Related Art
In general, liquid crystal display (LCD) devices are used in televisions, computers or portable devices. LCD devices use the optical anisotropy and polarization properties of liquid crystal molecules to generate a desired image. In particular, liquid crystal molecules can be aligned in a specific orientation, which can be controlled by applying an electric field across the liquid crystal molecules. Due to optical anisotropy, incident light is refracted according to the orientation of the liquid crystal molecules, thereby generating the desired image.
In addition, a LCD device generally includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel. A liquid crystal display panel generally includes gate lines and data lines intersecting each other. A liquid crystal cell is positioned at each area defined by intersections between the gate lines and the data lines. The liquid crystal display panel also includes pixel electrodes and a common electrode for applying an electric field within each of the liquid crystal cells. Each of the pixel electrodes is connected, via source and drain terminals of a thin film transistor as a switching device, to one of the data lines. A gate terminal of the thin film transistor is connected to one of the gate lines.
The driving circuit includes a gate driver for driving the gate lines, and a data driver for driving the data lines. The gate driver applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells row-by-row. The data driver applies a video signal to each data line whenever the scanning signal is applied to one of the gate lines. Thus, the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the video signal for each liquid crystal cell, thereby displaying an image. In general, in such a driving circuit, the gate driver generates a scanning signal for sequentially driving the gate lines using a shift register. In addition, the data driver generates a sampling signal for sequentially sampling video signals inputted from the exterior thereof by a certain unit using the shift register.
FIG. 1 is a schematic block diagram showing a configuration of the related art two-phase shift register. In FIG. 1, a two-phase shift register includes first to nth stages connected in cascade. The first to nth stages are commonly supplied with a clock signal C1, an inverted clock signal/C1, a high-level driving voltage (not shown), and a low-level driving voltage (not shown). In addition, a start pulse Vst is applied to the first stage while an output signal from each of the first to (n−1)th the stages is applied to a respective next stage. The 1st to nth stages have an identical circuit configuration, and sequentially shift a specific voltage of the start pulse Vst. The 1st to nth output signals Out1 to Outn are supplied as scanning signals for sequentially driving the gate lines of the liquid crystal display panel, or as sampling signals for sequentially sampling video signals within the data driver.
FIG. 2 is a detailed circuit diagram of one stage shown in FIG. 1. In FIG. 2, a stage includes an output buffer 20 having a fifth NMOS transistor T5 for outputting a clock signal C1 to an output line OUT under the control of a first node Q, a sixth NMOS transistor T6 for outputting a low-level driving voltage VSS to the output line OUT under the control of a second node QB, and a controller 10 having first to fourth NMOS transistors T1 to T4 for controlling the first and second nodes Q and QB. The stage is supplied a high-level driving voltage VDD, a low-level driving voltage VSS, the start pulse Vst, the clock signal C1, and the inverted clock signal/C1.
FIG. 3 is a driving waveform diagram of the stage shown in FIG. 2. As shown in FIG. 3, during a first period A, the inverted clock signal/C1 is at a high state, thereby turning on the first transistor T1 and resulting a high-state of the start pulse Vst being applied to the first node Q. Thus, the fifth transistor T5 is turned on and applies a low state voltage of the clock signal C1 to the output line OUT. In addition, the high-level inverted clock signal/C1 turns on the second transistor T2, thereby resulting the high-level driving voltage VDD be applied to the second node QB. Thus, the sixth transistor T6 is turned on and applies the low-level driving voltage Vss to the output line OUT. As a result, during the first period A, the stage outputs a low-state output signal OUT.
During a second period B, the inverted clock signal/C1 is at a low state, thereby turning off the first transistor T1 and floating the first node Q at a high state. Thus, the fifth transistor T5 remains turned on. In addition, the clock signal C1 is at a high state and the floated first node Q is boot-strapped due to an effect of a second parasitic capacitor CGS (shown in FIG. 2). Accordingly, a voltage at the first node Q may be raised to certainly turn on the fifth transistor T5, thereby rapidly supplying a high-state voltage of the first clock signal C1 to the output line OUT. At the same time, the high-level clock signal C1 turns on the third transistor T3. The fourth transistor T4 also is turned on by the boot-strapped first node Q, thereby applying the low-level driving voltage VSS to the second node QB. Thus, the sixth transistor T6 is turned off. As a result, during the second period B, the stage outputs a high-state output signal OUT.
During a third period C, the inverted clock signal/C1 is at the high state, thereby turning on the first transistor T1 and resulting a low-state voltage of the start pulse Vst being applied to the first node Q. Thus, the fifth transistor T5 is turned off. At the same time, the high-state inverted clock signal/C1 turns on the second transistor T2, thereby applying the high-level driving voltage VDD to the second node QB. Thus, the sixth transistor T6 is turned on and applies the low-level driving voltage VSS to the output line OUT. In addition, the third transistor T3 is turned off by a low-level clock signal C1, and the fourth transistor T4 is turned off by the low-level first node Q. As a result, during the third period C, the stage outputs the low-state output signal OUT.
During a fourth period D, the inverted clock signal/C1 is at a low state, thereby turning off the first and second transistors T1 and T2. Thus, the first node Q floats to its previous low state, to thereby turn off the fifth transistor T5. Thus, the fourth transistor T4 is turned off by the low-level first node Q. At the same time, the high-level first clock signal C1 turns on the third transistor T3. Thus, the second node QB node floats at a high state somewhat lowered than the high-level driving voltage VDD supplied in the previous period C. Accordingly, the sixth transistor T6 is turned on and applies the low-level driving voltage VSS to the output line OUT. As a result, during the fourth period D, the stage may output the low-state output signal OUT.
However, since each of the first to sixth NMOS transistors T1 to T6 formed by an amorphous silicon thin film transistor process has a structure in which the gate electrode/terminal overlaps the source and drain electrodes/terminals thereof, it inevitably includes parasitic capacitors CGD and CGS. Moreover, as sizes of the fifth and sixth NMOS transistors T5 and T6 are considerably enlarged to compensate a low mobility of the amorphous silicon thin film transistor, values of the parasitic capacitors CGD and CGS also are increased.
Although the parasitic capacitor CGS formed at an overlapping portion between the gate electrode and the source electrode of the fifth NMOS transistor T5 aids the boot-strapping of the first node Q, the parasitic capacitor CGD formed at an overlapping portion between the gate electrode and the drain electrode of the fifth NMOS transistor T5 causes a problem. For example, the parasitic capacitor CGD varies a voltage at the floated Q node whenever the clock signal C1 transitioning from a low state into a high state and causes a swing in the output voltage Vout. As shown in FIG. 3, a voltage at the first node Q floated into a low state by the clock signal C1 transitioning into a high state in the D period is varied into a somewhat higher state. Hence, the output voltage Vout also slightly rises from a low-level voltage and has a distortion. Since the output voltage Vout distorted in this manner is used as an input of the next stage, as it goes through a number of stages, a distortion amount in the output voltage Vout increases and causes a significant error in the LCD device operation.